Another system verilog constraint problem - Base class contraint becoming invisible

 Let us walk through the following code.

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class base; rand bit [4:0] c; constraint c_x { c == 'd1; } function void display(); this.randomize(); $display("Base c:%0d",c); endfunction endclass class derived extends base; rand bit [4:0] c; constraint c_x { c == 'd2; } function void display(); this.randomize(); $display("Derived c:%0d",c); super.display(); endfunction endclass module top; derived b; initial begin b = new; repeat(2) b.display(); end endmodule

In the above code, we have 2 classes, base and derived.

Base class has variable 'c' and constraint 'c_x', the same is replicated in the derived class as well.

we have 'display' function which is used to randomize the variable and print the value. In the derived in addition to it , a super.display() was called to print the base class variable value.

When you have 2 constraints with the same name on the same variable, the constraint in the base class becomes invisible and is not applied when the variable is randomized.

Simulation results:

Contains Synopsys proprietary information.
Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1; Apr 22 00:47 2021
Derived c:2
Base c:27
Derived c:2
Base c:7
V C S S i m u l a t i o n R e p o r t

Reference ( comments by experts )

https://verificationacademy.com/forums/systemverilog/how-constraint-executed