Showing posts with label corner cases. Show all posts
Showing posts with label corner cases. Show all posts

Sunday, April 18, 2021

The importance of targetted stimulus to expose corner cases

Lets take a scenario where an Interrupt is triggered whenever a JUMBO packet is observed on a port. 

In general an interrupt service routine is performed after receiving an interrupt and the status register which indicates the interrupt is cleared by writing 1 into it.

The interrupt is serviced , the register is cleared and we wait for the next event.

What if another JUMBO packet is received at the same time a write is issued to clear the register?

Sometimes the documentation (requirement specification) is not thorough and might miss the scenario on handling such cases.

It is important for us to generate all the possible cases and see how the system behaves under such cases and report it for confirmation.

In the current context, the event that triggers the interrupt should will been given more importance and  instead of clearing the register should have retained the interrupt status ( to 1).

These corner cases sometimes take multiple iterations for us to reach the scenario ( with random stimulus ).


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