module my_mod ( input clk, input rst );
endmodule: my_mod
module dut ( input clk, input rst );
genvar i;
generate
for(i=0;i<2;i++) begin: gen_my_mod
my_mod u_my_mod ( .clk(clk), .rst(rst) );
end
endgenerate
endmodule
module bind_x ( input clk, input rst );
endmodule: bind_x
module tb;
bit clk;
bit rst;
dut u_dut ( .clk(clk), .rst(rst) );
bind u_dut.gen_my_mod[0].u_my_mod bind_x bind_inst (.clk(clk), .rst(rst));
bind u_dut.gen_my_mod[1].u_my_mod bind_x bind_inst (.clk(clk), .rst(rst));
endmodule: tb
Showing posts with label SV BINDS. Show all posts
Showing posts with label SV BINDS. Show all posts
Tuesday, September 17, 2024
How to bind multiple instances of module inside DUT
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