There may be cases where you need to cover a range of values in a particular vector.
One such example is given below.
Address range : 0 -15 (addr)
Cover all even addresses in addr.
This was asked in an interview with cadence.
Code :
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 | module top; bit clk; bit [3:0] addr; covergroup cg_addr; cp: coverpoint addr[3:1] iff(addr[0] == 0); endgroup cg_addr cg; initial begin cg = new; clk <= 'b0; forever #5 clk = !clk; end initial begin repeat(16) begin @(posedge clk); addr++; cg.sample(); end $display("Coverage:%0f%%",cg.get_inst_coverage()); $finish; end endmodule |
* In the above code, we simply covered [3:1] vector range when addr[0] == 0 ( indicating that address is divisible by 2, even range ).
* We used the auto bins generated ( by default ).
Run the following commands:
vcs -sverilog -R cov.sv -cm line+cond+tgl
Result:
VCS Coverage Metrics Release L-2016.06 Copyright (c) 1991-2016 by Synopsys Inc.
Coverage:0.000000%
$finish called from file "cov.sv", line 24.
$finish at simulation time 155
---------------------------------------------------------------------------
VCS Coverage Metrics: during simulation line, cond, tgl was monitored
---------------------------------------------------------------------------
Coverage status: End of All Coverages ...
V C S S i m u l a t i o n R e p o r t
Time: 155
CPU Time: 0.400 seconds; Data structure size: 0.0Mb
I find it weird, get_inst_coverage() shows 0%, in other simulators the result is 100%
Mentor Questa sim:
# Loading work.top(fast)
#
# vsim -voptargs=+acc=npr
# run -all
# Coverage:100.000000%
# ** Note: $finish : testbench.sv(26)
# Time: 155 ns Iteration: 1 Instance: /top
# End time: 00:16:22 on Apr 15,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
Done
To generate the urgReport:
urg -dir *.vdb
firefox urgReport/grp0.html
Result:
Summary for Variable cp
CATEGORY EXPECTED UNCOVERED COVERED PERCENT
Automatically Generated Bins 8 0 8 100.00
Automatically Generated Bins for cp
Bins
NAME COUNT AT LEAST
auto[0] 1 1
auto[1] 1 1
auto[2] 1 1
auto[3] 1 1
auto[4] 1 1
auto[5] 1 1
auto[6] 1 1
auto[7] 1 1