Showing posts with label GLS. Show all posts
Showing posts with label GLS. Show all posts

Saturday, July 18, 2020

X propagation in ASIC/FPGA simulations

Ternary operator is used as a program statement.
If-else is a programming block.
Both can achieve similar results when a non 'X' or 'Z' value is used in conditional expression.
But when X is present inside conditional expression, the scenario changes.

Let us look at 3 scenarios.

When conditional expressions has 'bxx, 'bx0, 'bx1 values.

=========================================================================
module top;
  logic [1:0] a;
  logic [1:0] b;
  logic [1:0] c;
  logic [1:0] d;
  logic [1:0] e;
  
  initial begin
    b = 'bxx;
    c = 'b10;
    d = 'b11;
    
    a = b ? c : d;
    if(b) e = c;
    else  e = d;
    $display("Outputs - A:%0b E:%0b  || Condition:%0b || Inputs - C:%0b D:%0b",a,e,b,c,d);

    b = 'bx0;
    a = b ? c : d;
    if(b) e = c;
    else  e = d;
    $display("Outputs - A:%0b E:%0b  || Condition:%0b || Inputs - C:%0b D:%0b",a,e,b,c,d);

    b = 'bx1;
    a = b ? c : d;
    if(b) e = c;
    else  e = d;
    $display("Outputs - A:%0b E:%0b  || Condition:%0b || Inputs - C:%0b D:%0b",a,e,b,c,d);
  end
endmodule: top

===========================================================
Compiler version P-2019.06-1; Runtime version P-2019.06-1; Jul 18 06:15 2020

Outputs - A:1x E:11 || Condition:xx || Inputs - C:10 D:11
Outputs - A:1x E:11 || Condition:x0 || Inputs - C:10 D:11
Outputs - A:10 E:10 || Condition:x1 || Inputs - C:10 D:11

If you replace 'X' with 'Z' the result is the same.

Outputs - A:1x E:11 || Condition:zz || Inputs - C:10 D:11
Outputs - A:1x E:11 || Condition:z0 || Inputs - C:10 D:11
Outputs - A:10 E:10 || Condition:z1 || Inputs - C:10 D:11

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