Using GDB in simulation runs to debug C-code

When we run simulations with C-models (along with RTL and SV-UVM TB ) we might want to debug the C-code to identify issues.

Here is a list of commands for GDB ( for VCS )

1. gdb <SIMV absolute path>.
2. break <File_name>:<Line_number>
3. run <Simulation command line arguments>

These will allow you to to run the simulation until the debug point.

1. For executing line by line we can use <next>
2. For step, we can use <step>
3. To continue till next occurrence of  break point use <continue >
4. To print any variable with (print <var>)

Stuck at 0ns

Yesterday, I had an issue in one of my simulations, were the run was stuck at 0ns.Upon debug, I found an issue in the code. Although it looks obvious it takes quite a while to figure these out... Isolating the problem ....

module top;

  bit [2:0] cnt;

  initial begin

   for(cnt = 0; cnt <8;cnt++) $display("Cnt:%0d",cnt);

 end

endmodule

Look through the code, and we might feel it just prints 0...7 and the simulation stops.Once we run the code we realize that it gets stuck in an infinite loop.Reason is simple, the 'cnt' variable is a 3 bit variable, when the loop reaches 7 the 'cnt' is incremented and gets rounded of to 0, once again starting the loop , and this goes on and on.

 

System verilog constraints and OOPs

Does constraints of a parent class apply when child class handle is passed on to the later?

Code : 

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

class parent; rand int a; rand int b; constraint c_a { a == 10; } constraint c_b { b == 100; } function void display(); $display("Parent - A - %0d B - %0d ",a,b); endfunction endclass: parent class child extends parent; rand int a; constraint c_a { a == 20; } virtual function void display(); $display("Child - A - %0d B - %0d ",a,b); endfunction endclass class grand_child extends child; constraint c_a { a == 30; } function void display(); $display("Grand Child - A - %0d B- %0d ",a,b); endfunction endclass module top; parent p; child c; grand_child gc; initial begin p = new; c = new; gc= new; p = gc; void'(p.randomize()); void'(c.randomize()); void'(gc.randomize()); p.display(); c.display(); gc.display(); end endmodule

 

Here we have 2 cases, 

1. Case - 1 : Grand child handle 'gc' is assigned to parent handle 'p'. We have not used virtual key word in display function in parent, therefore limiting the scope to the parent int variables.

2. Case - 2 : Using virtual keyword in parent class function display(); 

Observation : 

• You can see from the print logs, that constraint of parent class on integer 'a' is not applied. we see a random integer value displayed instead of 10.
  
• Integer 'b' has constraint applied and therefore you see 100 in the print statement.
• Reason : since parent handle now contains the handle of grand child, the handling of both constraints differ, a is overridden ( in child class you have 'int a' re-declared )
• What if we use virtual keyword before display ? Now the scope of the display function is in grand child class, and there fore you can see 30 - 100
• What if you remove 'int a' in child class?
  

Without virtual keyword ( in parent display function ):

Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1; Nov 7 23:53 2020
Parent - A - -1360295855 B - 100
Child - A - 20 B - 100
Grand Child - A - 30 B- 100
V C S S i m u l a t i o n R e p o r t  

With virtual keyword ( in parent display function )

Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1; Nov 7 23:55 2020
Grand Child - A - 30 B- 100
Child - A - 20 B - 100
Grand Child - A - 30 B- 100
V C S S i m u l a t i o n R e p o r t  

Removing 'int a' in child class ( keep the constraint )

Compiler version Q-2020.03-SP1-1; Runtime version Q-2020.03-SP1-1; Nov 8 00:15 2020
Parent - A - 30 B - 100
Child - A - 20 B - 100
Grand Child - A - 30 B- 100
V C S S i m u l a t i o n R e p o r t