System verilog Assertion for back to back requests

Scenario :

A system generates request at random intervals in time.

Each request must be answered  by an acknowledgement after 1 to 10 cycles from request.

Following is the code to achieve the same.

bit clk,req,ack;  int v_req,v_ack;   function void inc_req();  req_cnt = req_cnt + 1'b1;  endfunction   property reqack_unique; int v_req; @(posedge clk) $rose(req), v_req=req_cnt, inc_req()) |-> ##[1:10] v_req ==v_ack ##0 ack;  endproperty   ap_reqack_unique: assert property(reqack_unique) v_ack = v_ack+1;  else v_ack=v_ack+1;