ASIC Design and Verification: UVM

UVM HEART_BEAT

The UVM heartbeat ( $uvm_heartbeat$ ) is a class in the Universal Verification Methodology (UVM) that acts as a watchdog timer to monitor the activity of components in a verification environment.

Its primary purpose is to detect simulation hangs or lockups early on, before the global simulation timeout is reached. This can save significant simulation time.

Here's a breakdown of how it works:

Watchdog Functionality: It provides a mechanism for environments to ensure their descendant components are still "alive" and actively contributing to the test.
Association with Objection: A $uvm_heartbeat$ object is associated with a specific objection object (specifically a $uvm_callbacks_objection$ ).
Heartbeat "Pulse" (Activity Check):
- A component being monitored by the heartbeat must raise or drop the associated objection during a defined "heartbeat window" or when a specific $uvm_event$ is triggered. This action is considered the "heartbeat" or a sign of activity.
- The monitoring process is typically started and triggered by a $uvm_event$ .
Failure Mechanism:
- If the $uvm_heartbeat$ monitor checks the activity (usually when its associated $uvm_event$ is triggered) and does not detect the required objection activity from the monitored components within the window, it issues a FATAL error and terminates the simulation. This signals a lock-up or stall condition.
Heartbeat Modes: The monitoring can be configured with different modes using the $set_mode$ method:
- $UVM_ALL_ACTIVE$ : Every monitored component must trigger the objection.
- $UVM_ANY_ACTIVE$ : At least one of the monitored components must trigger the objection.
- $UVM_ONE_ACTIVE$ : Exactly one of the monitored components must trigger the objection.

In essence, the $uvm_heartbeat$ ensures that critical components are making progress. If they stop, it assumes a hang and ends the test immediately.

CODE:

class component extends uvm_component;
  uvm_objection obj;
  `uvm_component_utils(component)
  
  function new (string name = "component", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
  endfunction
  
  task run_phase(uvm_phase phase);
    int i;
    repeat(3) begin
      #40;
      obj.raise_objection(this);
      `uvm_info(get_name(), $sformatf("raised objection for i = %0d", i), UVM_LOW)
      i++;
    end
  endtask
endclass

class base_test extends uvm_test;
  uvm_objection obj;
  component comp;
  uvm_component hb_comp[$];
  uvm_heartbeat hb;
  uvm_event hb_e;
  
  `uvm_component_utils(base_test)
  
  function new (string name = "base_test", uvm_component parent = null);
    super.new(name, parent);
  endfunction
  
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    obj = new("obj");
    comp = component::type_id::create("comp", this);
    hb = new("hb", this, obj);
    hb_e = new("hb_e");
    
    comp.obj = this.obj;
  endfunction
  
  task run_phase(uvm_phase phase);
    phase.raise_objection(this);
    
    hb.set_mode(UVM_ANY_ACTIVE);
    hb.set_heartbeat(hb_e,hb_comp);
    hb.add(comp);
    hb.start(hb_e);
    
    repeat(5) begin
      #50 `uvm_info(get_type_name(), $sformatf("triggering hb_e"), UVM_LOW)
      hb_e.trigger();
    end
    phase.drop_objection(this);
  endtask
endclass

module heartbeat_example();
  initial begin
    run_test("base_test");
  end
endmodule

RESULTS:

UVM_INFO @ 0: reporter [RNTST] Running test base_test...

UVM_INFO testbench.sv(18) @ 40: uvm_test_top.comp [comp] raised objection for i = 0
UVM_INFO testbench.sv(56) @ 50: uvm_test_top [base_test] triggering hb_e
UVM_INFO testbench.sv(18) @ 80: uvm_test_top.comp [comp] raised objection for i = 1
UVM_INFO testbench.sv(56) @ 100: uvm_test_top [base_test] triggering hb_e
UVM_INFO testbench.sv(18) @ 120: uvm_test_top.comp [comp] raised objection for i = 2
UVM_INFO testbench.sv(56) @ 150: uvm_test_top [base_test] triggering hb_e
UVM_INFO testbench.sv(56) @ 200: uvm_test_top [base_test] triggering hb_e
UVM_FATAL @ 200: uvm_test_top [HBFAIL] Did not recieve an update of obj on any component since last event trigger at time 150. The list of registered components is:
uvm_test_top.comp
UVM_INFO /apps/vcsmx/vcs/U-2023.03-SP2//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 200: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---

** Report counts by severity
UVM_INFO : 9
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 1
** Report counts by id
[HBFAIL] 1
[RNTST] 1
[UVM/RELNOTES] 1
[base_test] 4
[comp] 3

ASIC Design and Verification

Tuesday, October 7, 2025

UVM HEARTBEAT

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