Generating prime numbers between 1 to 100

 

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class test; int prime_q[$]; function void gen_prime(); for(int i=0;i<100;i++) begin if(is_prime(i)) prime_q.push_back(i); end $display("Prime:%p",prime_q); endfunction function bit is_prime(int n); if(n<2) return 0; for(int i=2;i<n;i++) begin if(n%i==0) return 0; end return 1; endfunction endclass module top; test t; initial begin t = new; void'(t.gen_prime()); end endmodule

OUTPUT:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Oct 16 07:02 2025
Prime:'{2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97}
V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.390 seconds; Data structure size: 0.0Mb
Thu Oct 16 07:02:15 2025

Single Linked List in System Verilog

 Lets code a simple singly Linked List which traverse from head to tail in one direction.

Requirement is simple, you will have a Node which contains two main elements, data and pointer to next node.

On adding a new node, the new node should create a handle of the old node and assign the pointer to the new one.

CODE:

class Node;
  int id;
  int data;
  Node next_node;
  
  function new ( int i );
    id = i;
    next_node = null;
  endfunction: new
  
  function void load_data ( int val );
    data = val;
  endfunction: load_data

  function void add_node ( Node node );
    node.next_node  = new(id);
    node.next_node  = this;
  endfunction: add_node
  
 endclass: Node
  
  module top;
    Node n[10];
    
    initial begin
      foreach ( n[i] ) begin
        n[i]      = new(i);
        n[i].data = $urandom_range(10,100);
        if(i>0) n[i].add_node(n[i-1]);           
      end 
      
      foreach ( n[i] ) begin        
        if(i==9) 
          $display ( "NODE ID:%0d Data:%0d NEXT_PTR:NULL", n[i].id,n[i].data );
        else 
          $display ( "NODE ID:%0d Data:%0d NEXT_PTR:%0d", n[i].id,n[i].data,n[i].next_node.id );
      end
    end        
  endmodule: top

RESULT:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Aug 12 10:17 2025
NODE ID:0 Data:54 NEXT_PTR:1
NODE ID:1 Data:62 NEXT_PTR:2
NODE ID:2 Data:68 NEXT_PTR:3
NODE ID:3 Data:44 NEXT_PTR:4
NODE ID:4 Data:75 NEXT_PTR:5
NODE ID:5 Data:88 NEXT_PTR:6
NODE ID:6 Data:89 NEXT_PTR:7
NODE ID:7 Data:72 NEXT_PTR:8
NODE ID:8 Data:62 NEXT_PTR:9
NODE ID:9 Data:53 NEXT_PTR:NULL
V C S S i m u l a t i o n R e p o r t

Constraint to have N elements distributed in M bins

Code to distribute N elements into M bins, you add unique keyword to have each bin will have unique number of elements.

class test;
  parameter int M = 5;
  parameter int N = 100;
  rand bit[31:0] arr[M];
  
  constraint c_arr { arr.sum() == N; foreach(arr[i]) { arr[i] inside {[0:N-1]}; } unique {arr}; }
  
  function void post_randomize();
    foreach(arr[i])
    $display("Array[%01d]:%02d\n",i,arr[i]);
  endfunction
  
endclass

module top;
  test t;
  
  initial begin
    t = new;
    void'(t.randomize());
  end
endmodule

RESULT:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 10:38 2024
Array[0]:23

Array[1]:01

Array[2]:10

Array[3]:11

Array[4]:15

Array[5]:21

Array[6]:14

Array[7]:03

Array[8]:02

Array[9]:00

V C S S i m u l a t i o n R e p o r t
Time: 0 ns
CPU Time: 0.430 seconds; Data structure size: 0.0Mb
Tue Sep 17 10:38:13 2024

How to kill a thread(s) in System Verilog

 The code use process class to kill the thread. 

class base;
  int id;
  
  task display();
    int x=0;
    for(int i=0;i<5;i++) begin 
      #10ns;
      x++;
      $display("%t BASE:%0d X:%0d",$time,id,x);
    end
  endtask

endclass

class test;
  process p[4];
  task run_phase();
    for(int i=0;i<4;i++) begin //{
      base b = new;
      fork: fork_p
        automatic base b1 = b;
        automatic int j = i;
        begin: run_d
          p[j] = process::self();
          b1.id = j;
          b1.display();
        end
      join_none
    end //}
    $display("%t Threads spawned",$time);
  endtask
  
endclass

module top;
  test t;
  
  initial begin
    t = new;
    fork
    t.run_phase();
    join_none
     #30ns;
    foreach(t.p[i]) t.p[i].kill();
  end
  
endmodule
  

Result:

Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64; Sep 17 10:31 2024
0 Threads spawned
10 BASE:0 X:1
10 BASE:1 X:1
10 BASE:2 X:1
10 BASE:3 X:1
20 BASE:0 X:2
20 BASE:1 X:2
20 BASE:2 X:2
20 BASE:3 X:2
V C S S i m u l a t i o n R e p o r t
Time: 30 ns
CPU Time: 0.370 seconds; Data structure size: 0.0Mb
Tue Sep 17 10:31:42 2024

System Verilog - Fork, Join

A common question in interviews for System Verilog is .... 

How do you come out of fork-join_none/any if 2 out of the 3 process in fork are complete.

Fork-join_any will wait until any one process is complete.

If you want to wait until any two process are complete, you can use semaphores or static variables inside each process and wait on the semaphore/variable for join_any/join_none statement.

One more questions revolving it is with fork_join.

You have 3 processes, and you need to come out of fork_join when 2 out of 3 process are complete. 

How to achieve this?

One way of doing it is using labels.

Check out....

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class test; static int cnt; task check_fork; fork begin: p1 #30;cnt++; $display("%t - Process-1 cnt:%d",$time,cnt); if(cnt==2) begin disable p3; disable p2; end end begin: p2 #40;cnt++; $display("%t - Process-2 cnt:%d",$time,cnt); if(cnt==2) begin disable p3; disable p1; end end begin: p3 #10;cnt++; $display("%t - Process-3 cnt:%d",$time,cnt); if(cnt==2) begin disable p2; disable p1; end end join $display("%t - Process-Complete cnt:%d",$time,cnt); endtask endclass: test module top; test s; initial begin s=new; s.check_fork; end endmodule: top

RESULT:

Chronologic VCS simulator copyright 1991-2021
Contains Synopsys proprietary information.
Compiler version S-2021.09; Runtime version S-2021.09; Apr 20 11:06 2023
10 - Process-3 cnt: 1
30 - Process-1 cnt: 2
30 - Process-Complete cnt: 2
V C S S i m u l a t i o n R e p o r t
Time: 30 ns
CPU Time: 0.560 seconds; Data structure size: 0.0Mb
Thu Apr 20 11:06:20 2023