Write a system verilog assertion to check for lock when '110' is observed on the input bit stream and lock is de-asserted when '111' is observed.

`timescale 1ns / 100ps
module top;
 bit a;
 bit [2:0] bin;
 bit lock;

 bit clk;

 initial begin
   $timeformat(-9,0,"ns",8);
   clk <= 0;
   forever #5 clk = !clk;
 end

 initial begin
   repeat(100) begin
     @(posedge clk);
     std::randomize(a);
   end
   $finish;
 end
  

 always @ (posedge clk) begin
   bin <= { bin[1:0], a };
   if(bin == 'b110) lock <= 1;
   if(bin == 'b111) lock <= 0;
 end


 property check_lock;
   @(posedge clk) (bin == 'b110) |=> lock throughout (bin == 'b111)[->1];
 endproperty

 property check_lock_deassertion;
   @(posedge clk) (bin == 'b111) && lock |=> $fell(lock);
 endproperty

 check_lock_assertion    : assert property (check_lock);
 check_lock_de_assertion : assert property (check_lock_deassertion);


 initial
   $monitor("%0t - Lock:%0d A:%0d B:%0b",$time,lock,a,bin);

  endmodule: top